The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or xe2x80x9cflip-chipxe2x80x9d packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is xe2x80x9cflippedxe2x80x9d over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, in some instances orienting the die with the circuit side face down on a substrate is disadvantageous. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
Techniques have been developed to access the circuit even though the integrated circuit (IC) is buried under the bulk silicon. For example, near infrared (nIR) microscopy is capable of imaging the circuit because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuit using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used.
Thinning the die for analysis of a flip chip bonded IC is usually accomplished by first globally thinning, wherein the silicon is thinned across the entire die surface. The silicon is globally thinned to allow viewing of the active circuit from the back side of the die using nIR microscopy. Mechanical polishing and chemical-mechanical polishing are two example methods for global thinning. Using nIR microscopy, an area is identified for accessing a particular area of the circuit.
Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuit, local thinning techniques can be used to thin an area smaller than the die size. One method of local thinning, referred to as Laser microchemical etching, is typically accomplished by focussing a laser beam on the back side of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone.
During failure analysis or for design debug of a flip chip die, accessing circuitry generally involves removing substrate from the back side of the die to access a node, or milling to the node and subsequently depositing a metal on the node. Often, global and local thinning processes as described above are used to accomplish such substrate removal. Accurate control of the substrate removal process, however, is not readily achieved. The global and local thinning processes described above often involve abrasive or otherwise damaging methods. When not controlled properly, removing substrate from the back side of a flip chip die can result in damage to or destruction of circuitry and other substrate in the device. In addition, as the substrate is thinned the amount of substrate remaining over circuitry in the device decreases, increasing the possibility for damage and making the proper control of the substrate removal process even more important.
Thinning of the back side of the die for accessing circuitry, though desirable, also involves certain part tolerances that must be addressed. One tolerance issue involves keeping the height of solder ball contacts on the die substantially uniform for every packaged device of a particular type. Even though the solder ball contacts have a tolerance requirement, when the solder is reflowed to attach the die to a package, the amount of change in height due to solder reflow can vary by several microns. The thickness of the die between the circuit side and back side is also subject to tolerance differences. Since the thickness of the starting silicon wafer is a non-essential parameter for making a functioning die, typically the die thickness is not known to an accurate level.
For instance, a typical die for a microprocessor may have a die thickness of 725xc2x115 microns. The end result is tolerance stacking due to the tolerances for the size of the solder balls, the height at which the die is attached and the thickness of the die. These tolerances stack up such that there can be tens of microns of difference in height from the top surface of the package to the top surface of the die among different packaged devices. Although this does not sound like much of a tolerance problem, it should be noted that the epitaxial layer is only between 2 and 10 microns thick. As a result, the thickness of the remaining silicon of a trench cannot be gauged by measuring from the top surface of the package to the bottom of the trench. Stack up of the tolerances of the various parts precludes simply xe2x80x9cmeasuring upxe2x80x9d from the package to which the die is attached to determine where the epitaxial layer containing the transistors begins. Simply put, such an approach is not accurate enough to prevent ruining the circuitry or transistors that must be analyzed or debugged. Once the circuitry or transistors are ruined, analysis or debugging is impossible.
Therefore, flip chip technology would benefit from a method and apparatus for conducting non-destructive testing and analysis of a portion of the active circuitry near the back side of the die that would eliminate the need for local thinning. By eliminating local thinning, failure analysis and debugging of the circuitry is facilitated without risking damage to the internal circuitry to be analyzed.
The method and system described herein is directed to determining a degree of substrate damage in an integrated circuit die. In an example embodiment there is described a method for detecting substrate damage in an integrated circuit die, having a back side and a circuit side, using magnetic resonance imaging. The back side of the die is first globally thinned down and a region for examination is selected. A magnetic field is applied to the selected region and then the region is scanned with a magnetic resonance imaging arrangement. A plurality of perturbations are measured to generate an array of perturbation signals, which are then converted to a local susceptibility map of the selected region of the die. The susceptibility map of the selected region is then examined to determine if there is any substrate damage.
Another example embodiment is directed to a system for detecting substrate damage in an integrated circuit die using a magnetic field detector arrangement. The system includes a mechanism for thinning the back side of the die and selecting a region for examination. In addition, an irradiation coil for irradiating a radio frequency magnetic field on the die to be examined is included as well as a detection coil disposed in the vicinity of the die, for detecting perturbations in the magnetic field from the die. The system includes a processor arrangement constructed to receive perturbations from the detection coil, convert the perturbations to perturbation signals and then digitize the signals. Finally, the system includes a computer arrangement that is programmed to process the digitized perturbation signals via a susceptibility algorithm, produce a susceptibility map and examine the susceptibility map for substrate damage.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.